1. Field of the Invention
The present invention relates to a method for forming an isolation layer in a semiconductor device, and more particularly, to a method for forming an isolation layer in a semiconductor device by which occurrence of an angular formation phenomenon at the edge portions in the upper and lower portions of a trench is reduced when a shallow trench isolation layer (hereinafter referred to as STI) is formed is prevented, so that the malfunction of the device and the deterioration of properties of the device due to a parasitic transistor and leakage current can be prevented.
Also, the present invention relates to a method for forming an isolation layer in a semiconductor device whereby a silicon nitride (SiN) layer is formed on the side wall of a pad oxide film and on the surface of a silicon (Si) trench by a nitrogen (N+) plasma nitrification process after conducting a trench etching process for forming STI, so that the generation of a moat is prevented and the deterioration in performance of the device is prevented.
2. Description of the Related Art
In general, with the advance of semiconductor technology and further high speed and high integration of a semiconductor device, a need for a fine pattern increases and a highly accurate pattern value is also required. Such a trend is applied to a semiconductor isolation area occupying a large space in a semiconductor device.
Currently, a LOCOS (local oxidation of silicon) oxide film is mainly used as an isolation layer of a semiconductor device. The LOCOS type isolation layer is obtained by selectively and partially oxidizing a substrate. However, the LOCOS type isolation layer is disadvantageous because a bird""s beak phenomenon occurs at the edge thereof so that area of the isolation layer increases and current leakage is generated.
The use of an STI type isolation layer having a narrow width and exhibiting a superior isolation property has been suggested. The conventional STI isolation layer forming method is shown in FIG. 1.
Referring to FIG. 1, a pad oxide film 12 serving as a buffer and a pad nitride film 14 for restricting oxidation are formed in order on a silicon substrate 10. Next, a resist pattern (not shown) for exposing an expected isolation area is formed on the pad nitride film 14. Here, the resist pattern is formed by using a DUV (deep ultraviolet) light source exhibiting a high resolution to form an isolation layer having a narrow width. Then, the pad nitride film 14, the pad oxide film 12, and the silicon substrate 10 are etched to a predetermined depth by using the resist pattern as a mask, forming a shallow trench 16. Next, the resist pattern is removed by a well-known method and the shallow trench 16 is filled with an oxide film 18. Next, the pad nitride film 14 and the pad oxide film 12 remaining on the surface of the semiconductor substrate 10 are removed by a well-known method, and thus, an STI isolation layer is completed.
FIGS. 2A through 2C are sectional views explaining problems associated with the conventional STI isolation layer forming method. FIG. 2A shows that the pad oxide film 12 is wet etched and a pad oxide film undercut 12c is generated during a cleaning process for forming the conventional STI isolation layer. However, a problem occurs in that the pad oxide film undercut 12c is not completely filled when the shallow trench 16 is filled with the insulation film 18.
FIG. 2B shows that a void 12v is generated in the insulation film 18 embedded through the pad oxide film undercut 12c of FIG. 2A. FIG. 2C shows that a moat 12m is generated due to the void 12v when the oxide film 18 is made planar in a chemical-mechanical polishing (CMP) process. In the semiconductor device where the moat 12m is generated, the thickness of a gate electrode deposited to the moat 12m selectively increases so that etch residue is generated during a gate etching process.
Also, when wall oxidation is performed in an atmosphere of oxygen (O2), a very large compression stress is applied to an edge portion of the upper portion of the trench because the pad nitride film 14, the pad oxide film 12, and the silicon substrate 10 form boundary surfaces. Accordingly, the speed of diffusion of oxygen is slow and the crystallization surfaces of silicon exist differently at the edge portion of the lower portion of the trench (a trench bottom surface 100, a trench side surface 110, and a trench lower edge portion 111), so that the speeds of oxidation in a horizontal direction and a vertical direction are different from each other. As a result, an angular formation phenomenon is generated at the edge portions of the upper and lower portions of the trench. When the angular formation phenomenon is generated, a gate oxide film thinning phenomenon is induced so that a hump phenomenon (a phenomenon in which drain current irregularly varies at a certain drain voltage) is generated at a drain current and drain voltage feature of a transistor. Also, when a power voltage Vcc needed for operation of the device is applied to the gate, an electric field concentration effect, that is, the size of the electric field at the edge portion of the trench is selectively increased, is generated. Thus, leakage current increases and the GOI (gate oxide integrity) property of the device deteriorates.
To solve the above problems, it is an objective of the present invention to provide a method for forming an isolation layer in a semiconductor device wherein occurrence of the angular formation phenomenon at the edge portions of the upper and lower portions of the trench during formation of a shallow trench isolation layer, (STI) is prevented, so that malfunction of the device and deterioration of performance due to a parasitic transistor and leakage current can be prevented.
Also, it is another objective of the present invention to provide a method for forming an isolation layer in a semiconductor device wherein silicon nitride films are formed at the side wall of the pad oxide film and the surface of trench silicon through a nitrogen (N+) plasma nitrification process, after a trench etching process for formation of STI, so that generation of a moat is restricted and deterioration of the device is prevented.
Accordingly, to achieve the above objective, there is provided a method for forming an isolation layer in a semiconductor device comprising the steps of forming a pad oxide film in a wet oxidation process on a silicon substrate, forming a pad nitride film in a low pressure chemical vapor deposition process on the pad oxide film, forming a shallow trench by etching the pad nitride film, the pad oxide film and the silicon substrate to a predetermined depth, forming a silicon nitride film in a nitrogen plasma nitrification process on the inner wall of the trench, filling the trench where the silicon nitride film is formed with an oxide film, and planarizing the pad nitride film and the pad oxide film in a chemical-mechanical polishing process so that the silicon substrate can be exposed.
It is preferred in the present invention that the conditions of the pad oxide film depositing process are a process temperature of 800-900xc2x0 C., a process pressure of 1-2.5 Torr, a mixing ratio of water (H2O) and nitride oxide (N2O) of 130-200, a sccm of 70-90 sccm, and a thickness of the pad oxide film of 50-150.
Also, it is preferred in the present invention that, in the low pressure chemical vapor deposition process, a compression stress of a boundary surface between the pad oxide film and the pad nitride film is maintained at 102-103 dyne/cm or less by controlling the chemical composition ratio with Si3N4, so that a lifting phenomenon of the pad nitride film can be restricted.
Also, it is preferred in the present invention that the conditions of the pad nitride film depositing process are: a process temperature of 700-900xc2x0 F., a process pressure of 2.5-4 Torr, a mixing ratio of SiH4 and N2O of 120-150, a sccm of 150-180 sccm, and a thickness of the pad nitride film of 1000-13000 xc3x85.
Also, it is preferred in the present invention that the angle between the bottom surface and side surface of the trench 35 is 80-85xc2x0 C. and the depth of the trench is 1000-5000 xc3x85.
Also, it is preferred in the present invention that etch damage accumulated during the trench etching is removed by performing a wall sacrificial oxidation process in a wet method after the trench etching process.
Also, it is preferred in the present invention that the process conditions of the wall sacrificial oxidation process performed in a wet method are a process temperature of 800-900xc2x0 F., a process pressure of 1.8-4 Torr, a mixing ratio of H2O and N2O gases of 120-140, a sccm of 80-100 sccm, and a thickness of the wall sacrificial oxidation film of 50-200 xc3x85.
Also, it is preferred in the present invention that etch damage accumulated during the trench etching is removed by performing a wall sacrificial oxidation process in a dry method after the trench etching process.
Also, it is preferred in the present invention that the process conditions of the wall sacrificial oxidation process performed in a dry method are a process temperature of 950-1050xc2x0 C., a process pressure of 1.2-2.2 Torr, a mixing ratio of N2O and O2 gases of 110-140, a sccm of 180-230 sccm, and a thickness of the wall sacrificial oxidation film of 50-200 xc3x85.
Also, it is preferred in the present invention that the thickness of the silicon nitride film is 30-50 xc3x85.
Also, it is preferred in the present invention that the conditions of the nitrogen plasma nitrification process are a process pressure of 20-30 mTorr, a high frequency (RF) electric power of 150-250 kW, a high frequency (RF) of 13.56 MHz, and a speed of flow of nitrogen (N2) gas of 100-150 sccm.
Also, it is preferred in the present invention that the density of combination of a boundary surface between the silicon nitride film and the silicon substrate is controlled to be 102-103 atom/cm3 or less.
Also, it is preferred in the present invention that, to increase the attachment strength between the oxide film and the silicon substrate, a wall sacrificial oxidation process using a wet method is performed.
Also, it is preferred in the present invention that the process conditions of the wall sacrificial oxidation process performed in a wet method are a process temperature of 800-850xc2x0 C., a process pressure of 1.2-3 Torr, a mixing ratio of H2O and N2O gases of 120-140, a sccm of 80-100 sccm, and a thickness of the wall sacrificial oxidation film of 50-200 xc3x85.
Also, it is preferred in the present invention that, to increase the attachment strength between the oxide film and the silicon substrate, a wall sacrificial oxidation process using a dry method is performed.
Also, it is preferred in the present invention that the process conditions of the wall sacrificial oxidation process performed in the dry method are a process temperature of 900-1000xc2x0 C., a process pressure of 1.8-3.3 Torr, a mixing ratio of N2O and O2 gases of 120-150, a sccm of 80-110 sccm, and a thickness of a wall sacrificial oxidation film of 50-200 xc3x85.
Also, it is preferred in the present invention that the oxide film is a high density plasma oxide film.
Also, it is preferred in the present invention that an annealing process is performed after the inside of the trench is filled with the oxide film.
Also, it is preferred in the present invention that the annealing process is performed under the conditions of a mixing ratio of nitrogen (N2) and argon (Ar) of 100-140, a sccm of 100-120 sccm, a process temperature of 900-1000xc2x0 C., and a process pressure of 1.5-3 Torr.